Analysis of Charge Reuse in Switched-Capacitor Power-Converter Drivers

被引：0

作者：

Lipski, Mark ^{[1
]}

Gregori, Stefano ^{[1
]}

机构：

[1] Univ Guelph, Sch Engn, Guelph, ON N1G 2W1, Canada

来源：

2019 IEEE 62ND INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2019年

关键词：

Adiabatic circuit; charge redistribution; charge reuse; parasitic capacitance; energy efficiency; DESIGN;

D O I：

10.1109/mwscas.2019.8884823

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a method of reducing the power lost when driving the gate capacitance of CMOS transistors in switched-capacitor power converters. The consequences of the increased rise and fall times on the transistor on resistance are investigated. Additionally, the effectiveness of charge reuse on the transistors of a switched-capacitor voltage doubler is simulated in 65-nm CMOS technology resulting in efficiency improvements.

引用

页码：742 / 745

页数：4

共 6 条

[1] Charge Reusing in Switched-Capacitor Voltage Multipliers with Reduced Dynamic Losses [J].