Fast and Accurate Code Placement of Embedded Software for Hybrid On-chip Memory Architecture

被引:0
|
作者
Zhou, Zimeng [1 ]
Ju, Lei [1 ]
Jia, Zhiping [1 ]
Li, Xin [1 ]
机构
[1] Shandong Univ, Sch Comp Sci & Technol, Jinan, Shandong, Peoples R China
来源
2014 IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2014 IEEE 6TH INTL SYMP ON CYBERSPACE SAFETY AND SECURITY, 2014 IEEE 11TH INTL CONF ON EMBEDDED SOFTWARE AND SYST (HPCC,CSS,ICESS) | 2014年
关键词
SCRATCH-PAD MEMORY; ALLOCATION; ALGORITHMS; SYSTEMS;
D O I
10.1109/HPCC.2014.169
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Onchip SRAMs including scratchpad memories (SPMs) and caches are widely used in embedded systems to narrow the speed gap between CPU and memory. Memory subsystem acts as both performance and energy bottleneck for many applications in many contemporary embedded systems. While many off-the-shelf embedded processors employ the architecture with hybrid caches and SPMs on-chip memories, many existing work on SPM management ignore the synergy between caches and SPMs. In this work, we propose static SPM allocation strategy for the above-mentioned system architecture with the objective of minimizing the overall instruction memory subsystem latency and/or energy consumption. We capture the cache conflict misses with a fine-grained temporal cache behavior model. We propose an approximate knapsack based heuristic algorithm to generate an outstanding function-level SPM allocation which favors fast design space exploration. Compared with the state-of-the-art SPM heuristic allocation strategy, experimental results show that our SPM management scheme achieves 14.00% further improvement in instruction memory subsystem performance, and up to 17.69% in terms of energy saving.
引用
收藏
页码:1008 / 1015
页数:8
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