Equalizer implementation for 10 gbps serial data link in 90 nm CMOS technology

This paper presents a 10-Gbps SerDes equalizer using 90-nm standard CMOS technology. It is would be integrated into ASIC designs that require serial link transceivers. The equalizer used to overcome the effects of channel loss and intersymbol interference (ISI), these effects result from the reflections and the finite channel bandwidth. The transmitter features a 4 tap feed forward equalizer (FFE) that can supply up to 800 mV peak-to-peak differential on 100-Ohm differential termination. The receiver employs a 4 tap adaptive decision feedback equalizer (DFE) in a speculative approach. The adaptation uses a modified form of the LMS algorithm. High speed circuits were implemented using CML topology. Both the transmitter and receiver use half rate architecture. The equalizer power consumption is 22.2 mW at a supply voltage of 1.2 V.