0.35 dB Loss 20 dB Coupling Directional Coupler Integrated in 130 nm CMOS SOI Technology targeting 3G PA SOC

RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning FEM integration on silicon [1]. In this quest, SOI technology has already emerged as a promising one enabling the integration of low cost antenna switches [2]. Clearly, Power Amplifier (PA) integration on CMOS is the next step and SOI technology is an appealing solution because of the integration capability of switches. In this paper, we investigate the feasibility to integrate on CMOS SOI a key passive function for PA: low loss directional coupler. A 700 MHz-1 GHz directional coupler has been achieved with insertion losses lower than 0.35 dB in the band, demonstrating the suitability of CMOS SOI technology to integrate single die PA solutions.