Si via interconnection technique for 3D MEMS package

被引：0
|
作者：
Jeong, Jinwoo [1 ]
Kim, Hyeon Cheol [1 ]
Chun, Kukjin [1 ]
Lee, Eunsung [2 ]
Moon, Changyoul [2 ]
机构：
[1] Seoul Natl Univ, Sch Elect Engn & Comp Sci, Seoul, South Korea
[2] Samsung Adv Inst Technol, Seoul, South Korea
来源：
2006 IEEE SENSORS, VOLS 1-3 | 2006年
关键词：
D O I：
暂无
中图分类号：
O42 [声学];
学科分类号：
070206 ; 082403 ;
摘要：
A novel Si via interconnection technique using the doped silicon as an interconnection material is presented for 3D MEMS package. Concept and key idea of silicon via is described. Two layers stacked via arrays with 40 mu m and 50 mu m spacing are fabricated to prove its feasibility. SDB (Silicon Direct Bonding) multi-stacking process is used for fabrication of stacked package, which consists of a substrate, MEMS structure layer and a cover layer. Resistance of the via which has 34 mu m width is measured. Additional electrical and mechanical characteristics of fabricated via are under testing.
引用
收藏
页码：1155 / +
页数：2
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