共 24 条
[2]
Cintra M, 2000, PROCEEDING OF THE 27TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, P13, DOI [10.1145/342001.363382, 10.1109/ISCA.2000.854373]
[3]
EKANADHAM K, 1998, P 4 INT S HIGH PERF
[4]
FIGUEIREDO R, 2001, P INT C PAR PROC SEP
[5]
FRANK M, 2001, MITLCSTM619
[7]
Tradeoffs in buffering memory state for thread-level speculation in multiprocessors
[J].
NINTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS,
2003,
:191-202
[8]
Speculative versioning cache
[J].
1998 FOURTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS,
1998,
:195-205
[9]
GUPTA M, 1998, P SUP 1998 NOV
[10]
HAGERSTEN E, 1999, P 5 INT S HIGH PERF