Algorithm and Hardware Implementation for Generation of Low Power SIC Test Sequences

被引:0
作者
Cao, Bei [1 ,2 ]
Wen, Dianzhong [1 ]
Li, Zhiyuan [1 ]
Zhang, Yichao [1 ]
Cao, Bei [1 ,2 ]
机构
[1] Heilongjiang Univ, Elect Sci & Technol Post Doctoral Res Ctr, Harbin, Peoples R China
[2] Heilongjiang Univ, Minist Educ, Developing Key Lab Sensing Technol & Syst Cold Re, Harbin, Peoples R China
来源
2015 FIFTH INTERNATIONAL CONFERENCE ON INSTRUMENTATION AND MEASUREMENT, COMPUTER, COMMUNICATION AND CONTROL (IMCCC) | 2015年
关键词
BIST; low power testing; SIC test sequences; SSIC test sequences;
D O I
10.1109/IMCCC.2015.192
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Single input change (SIC) test sequences have been investigated in recent years because it is effective to more test fault types and test power reduction. In this paper, generation of sequential SIC (SSIC) test sequences based on deterministic built-in self-test (BIST) is proposed for decreasing the test power consumption and test application time with high test fault coverage. Furthermore, several important properties of SSIC sequences are presented and discussed as the basic of seed selection. Proper selection of SIC seeds is the key technique to a successful deterministic BIST. The seeds of SSIC are generated using the properties of SSIC. A hardware structure is designed to generate SSIC sequences. Experimental results based on ISCAS'85 Benchmark circuits demonstrate that the proposed SSIC test sequences can reduce test power consumption and test application time than random SIC (RSIC) test sequences, and also keeping high test fault coverage.
引用
收藏
页码:881 / 884
页数:4
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