Evaluation of a Hardware Transactional Memory Model in an NoC-based Embedded MPSoC

被引：0

作者：

Kunz, Leonardo ^{[1
]}

Girao, Gustavo ^{[1
]}

Wagner, Flavio R. ^{[1
]}

机构：

[1] Univ Fed Rio Grande do Sul, Inst Informat, BR-91501970 Porto Alegre, RS, Brazil

来源：

SBCCI 2010: 23RD SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2010年

关键词：

Transactional Memory; Hardware; Embedded Systems; NoC;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Transactional memories have emerged in the last years as a new solution for synchronization on shared memory multiprocessors helping to exploit the parallelism of applications while overcoming limitations of the lock mechanism. This paper presents the performance and energy evaluation of a hardware transactional memory (HTM) solution in an NoC-based MPSoC environment, comparing it to a traditional shared memory model that uses locks to provide consistency. Experiments show that transactional memory is a promising alternative to locks for future NoC-based embedded systems, resulting in performance gains up to 30% and energy savings up to 32%, depending on the application and on the architecture configuration.

引用

页码：85 / 90

页数：6