Design and performance analysis of Dual-Gate All around Core-Shell Nanotube TFET

被引：57

作者：

Kumar, Naveen ^{[1
]}

Mushtaq, Umar ^{[2
]}

Amin, S. Intekhab ^{[3
]}

Anand, Sunny ^{[2
]}

机构：

[1] Dr BR Ambedkar Natl Inst Technol Jalandhar, Jalandhar, Punjab, India

[2] Amity Univ, Sect 125, Noida, Uttar Pradesh, India

[3] Jamia Milia Islamia, New Delhi, India

来源：

SUPERLATTICES AND MICROSTRUCTURES | 2019年 / 125卷

关键词：

Nanotube; Dual-Gate All around; Nanowire; Core and shell gates; TFET; FIELD-EFFECT TRANSISTORS; TUNNEL-FETS;

D O I：

10.1016/j.spmi.2018.09.012

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

In this research work, we have put forward Silicon based Nanotube structure with Dual Gate All around configuration. The proposed device has been compared with Conventional Nanowire structure and the comparison is concocted on account of analog parameters of both the devices. The structural parameters of both the devices are kept identical like work function, doping concentrations of Source, Channel and Drain regions. By using an inner core gate and an outer shell gate, the proposed device exhibited superior Analog characteristics over its Nanowire counterpart in terms of drive current (ION), Electrical criteria, capacitance, unity gain, and transconductance.

引用

页码：356 / 364

页数：9

共 43 条

[1] Design and Performance Analysis of Core-Shell Dual Metal-Dual Gate Cylindrical GAA Silicon Nanotube-TFET
Umar Mushtaq
Naveen Kumar
Sunny Anand
Intekhab Amin
Silicon, 2020, 12 : 2355 - 2363
[2] Design and Performance Analysis of Core-Shell Dual Metal-Dual Gate Cylindrical GAA Silicon Nanotube-TFET
Mushtaq, Umar
Kumar, Naveen
Anand, Sunny
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SILICON, 2020, 12 (10) : 2355 - 2363
[3] Gate-All-Around Nanowire TFET with Heterojunction and Core Insulator: Design and Analysis
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[4] Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application
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[5] Optimization of InAs/GaSb core-shell nanowire structure for improved TFET performance
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[6] Performance analysis of gate all around GaAsP/A1GaSb CP-TFET
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SUPERLATTICES AND MICROSTRUCTURES, 2018, 117 : 364 - 372
[7] An extensive electrostatic analysis of dual material gate all around tunnel FET (DMGAA-TFET)
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ADVANCES IN NATURAL SCIENCES-NANOSCIENCE AND NANOTECHNOLOGY, 2016, 7 (02)
[8] Design and Analysis of Junctionless-Based Gate All Around N plus Doped Layer Nanowire TFET Biosensor
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ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2024, 13 (01)
[9] Design and Performance Optimization of Novel Core-Shell Dopingless GAA-Nanotube TFET With Si0.5Ge0.5-Based Source
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IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (03) : 789 - 795
[10] An efficient low-power configured dual material gate-all-around nanotube TFET with hetero-dielectric layers
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PHYSICA SCRIPTA, 2025, 100 (05)

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