Delay Locked Loop with linear delay element

被引：0
|
作者：
Jovanovic, G [1 ]
Stojcev, M [1 ]
Krstic, D [1 ]
机构：
[1] Fac Elect Engn, Nish 18000, Serbia Monteneg
来源：
Telsiks 2005, Proceedings, Vols 1 and 2 | 2005年
关键词：
DLL; CMOS circuits design; delay;
D O I：
暂无
中图分类号：
TN [电子技术、通信技术];
学科分类号：
0809 ;
摘要：
Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) are used in synchronous digital systems in order to improve timings, i.e. to minimize negative effects of skew and jitter in the clock distribution network. In this paper, we propose an efficient DLL architecture implemented with linear delay element. Linearization is achieved by modifying the classical hardware structures of the bias and charge pump circuits [1]. Namely, in our proposal both circuits, instead of single ended use differential input/output structure. This allows us to realize process independent and temperature compensated DLL circuit. Simulation results, that relate to models of 1.2 mu m CMOS double-poly, double-metal technology, show that the proposed DLL has linear delay regulation and stable lock-in for supply voltage, temperature, and parameter's technology process variations, in the full range of regulation.
引用
收藏
页码：397 / 400
页数：4
相关论文
共 50 条
  • [11] Hybrid DPWM with Analog Delay Locked Loop
    Shen, Xuzhen
    Wu, Xiaobo
    Lv, Jing
    Qin, Lin
    INTERNATIONAL MULTICONFERENCE OF ENGINEERS AND COMPUTER SCIENTISTS (IMECS 2010), VOLS I-III, 2010, : 1279 - 1281
  • [12] Phase interpolator using delay locked loop
    Kim, T
    Kim, B
    2003 SOUTHWEST SYMPOSIUM ON MIXED-SIGNAL DESIGN, 2003, : 76 - 80
  • [13] REDUCED COMPLEXITY DELAY-LOCKED LOOP
    WILDE, A
    ELECTRONICS LETTERS, 1995, 31 (23) : 1979 - 1980
  • [14] DYNAMICS AND STABILITY OF A DELAY-LOCKED LOOP
    ESTES, LE
    ONEILL, EL
    IEEE TRANSACTIONS ON AUTOMATIC CONTROL, 1976, 21 (04) : 564 - 567
  • [15] A semidigital dual delay-locked loop
    Sidiropoulos, S
    Horowitz, MA
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (11) : 1683 - 1692
  • [16] Fast locking delay-locked loop using initial delay measurement
    Kim, T
    Wang, SH
    Kim, B
    ELECTRONICS LETTERS, 2002, 38 (17) : 950 - 951
  • [17] Fractional-N multiplying delay-locked loop with delay-locked loop-based injection clock generation
    Jee, D. -W.
    ELECTRONICS LETTERS, 2016, 52 (09) : 694 - U86
  • [18] Low Power Delay Locked Loop with All Digital Controlled SAR Delay Cell
    Kuo, Ko-Chi
    Chang, Chung-Yuan
    Li, Si-Hsien
    2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2012, : 120 - 123
  • [19] An Analog Dual Delay Locked Loop Using Coarse and Fine Programmable Delay Elements
    Jasielski, Jacek
    Kuta, Stanislaw
    Machowski, Witold
    Kolodziejski, Wojciech
    MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, MIXDES 2013, 2013, : 185 - 190
  • [20] Delay length locked loop in target range tracking
    Balasubramanian, K
    Rajaravivarma, V
    PROCEEDINGS OF THE 33RD SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY, 2001, : 167 - 170
12345