A silicon BiCMOS single-chip UHF receiver design

被引：0

作者：

Xu, YS ^{[1
]}

Shi, CQ ^{[1
]}

Wei, J ^{[1
]}

Yu, H ^{[1
]}

Tao, YG ^{[1
]}

Hong, L ^{[1
]}

Lai, ZS ^{[1
]}

机构：

[1] E China Normal Univ, Inst Microelect Circuits & Syst, Shanghai 200062, Peoples R China

来源：

2005 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS: VOL 1: COMMUNICATION THEORY AND SYSTEMS | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A single-chip UHF receiver integrated with PLL working at ISM band from 290MHz to 470MHz is presented. It operates from a single 5V supply with a nominal current consumption of only 6.5 mA (with all parts of the receiver are active). The IC requires only a low frequency reference clock (Crystal Oscillator), a varactor diode, and a few of standard passive elements to operate fully, satisfying almost all of the low power radio regulations. The LNA has a 1.56dB noise figure, 15.2dB power gain and 8dBm IIP3. The mixer has a 9.3dB SSB noise figure with 5dBm IIP3. The PLL achieves a phase noise of -99.7dBc/Hz at 100KHz offset with 433MHz carrier frequency. The RF receiver was implemented in a 0.8um, 12GHzf(T) (NPN) Si BiCMOS production technology.

引用

页码：1295 / 1299

页数：5