TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET

被引：75

作者：

Sharma, Rupendra Kumar ^{[1
]}

Gupta, Mridula ^{[1
]}

Gupta, R. S. ^{[1
]}

机构：

[1] Univ Delhi, Dept Elect Sci, New Delhi 110021, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2011年 / 58卷 / 09期

关键词：

ATLAS device simulator; double-gate MOSFET (DG MOSFET); dual-material double gate (DMDG); gate-stack (GS) engineering; graded channel (GC); KAPPA GATE DIELECTRICS; STACK SON MOSFET; ANALOG PERFORMANCE; HOT-CARRIER; ARCHITECTURE; TRANSISTORS; SIMULATION; IMPACT; OPTIMIZATION; NMOSFET;

D O I：

10.1109/TED.2011.2160065

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the effect of various device design engineerings such as channel engineering, i.e., graded channel (GC), gate stack (GS) engineering (high-kappa), and dual-material gate (DMG) on double-gate MOSFET (DG MOSFET) have been analyzed using ATLAS device simulator. Furthermore, the combinations of these technologies i.e., GC, along with GS engineering, i.e., GCGSDG, and GS together with DMG, i.e., GS dual-material DG (GSDMDG), have been taken into consideration. The simulation results demonstrate that, out of the several design engineerings, the GCGSDG is the most suitable for high-speed switching applications. However, the GSDMDG provides superior performance as an amplifier.

引用

页码：2936 / 2943

页数：8

共 31 条

[1]

[Anonymous], 2003, ATLAS US MAN

[2] Optimization and realization of sub-100-nm channel length single halo p-MOSFETs [J].

Borse, DG ;

Rani, M ;

Jha, NK ;

Chandorkar, AN ;

Vasi, J ;

Rao, VR ;

Cheng, B ;

Woo, JCS .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (06) :1077-1079

[3] MOSFET transistors fabricated with high permitivity TiO2 dielectrics [J].

Campbell, SA ;

Gilmer, DC ;

Wang, XC ;

Hsieh, MT ;

Kim, HS ;

Gladfelter, WL ;

Yan, JH .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (01) :104-109

[4] Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: A review [J].

Chaudhry, A ;

Kumar, MJ .

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2004, 4 (01) :99-109

[5] Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping [J].

Chen, XD ;

Ouyang, QC ;

Wang, G ;

Banerjee, SK .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (11) :1962-1968

[6] Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's [J].

Cheng, BH ;

Cao, M ;

Vande Voorde, P ;

Greene, W ;

Stork, H ;

Yu, ZP ;

Woo, JCS .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (01) :261-262

[7] Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric [J].

Kang, L ;

Lee, BH ;

Qi, WJ ;

Jeon, Y ;

Nieh, R ;

Gopalan, S ;

Onishi, K ;

Lee, JC .

IEEE ELECTRON DEVICE LETTERS, 2000, 21 (04) :181-183

[8] Dual material double-layer gate stack SON MOSFET: A novel architecture for enhanced analog performance - Part I: Impact of gate metal workfunction engineering [J].

Kasturi, Poonam ;

Saxena, Manoj ;

Gupta, Mridula ;

Gupta, R. S. .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (01) :372-381

[9] Dual-material double-layer gate stack SON MOSFET: A novel architecture for enhanced analog performance - Part II: Impact of gate-dielectric material engineering [J].

Kasturi, Poonam ;

Saxena, Manoj ;

Gupta, Mridula ;

Gupta, R. S. .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (01) :382-387

[10] Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOICMOS [J].

Kim, SD ;

Park, CM ;

Woo, JCS .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (10) :1748-1754

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