A Maximum Logarithmic Maximum a Posteriori Probability Based Soft-Input Soft-Output Detector for the Coded Spatial Modulation Systems

被引:2
|
作者
Liu, Tsung-Hsien [1 ,2 ]
Jiang, Ting-Xu [3 ]
Chung, Ching-Che [4 ]
Chu, Yuan-Sun [2 ,3 ]
机构
[1] Natl Chung Cheng Univ, Dept Commun Engn, Chiayi 621301, Taiwan
[2] Natl Chung Cheng Univ, Adv Inst Mfg High Tech Innovat AIM HI, Chiayi 621301, Taiwan
[3] Natl Chung Cheng Univ, Dept Elect Engn, Chiayi 621301, Taiwan
[4] Natl Chung Cheng Univ, Dept Comp Sci & Informat Engn, Chiayi 62102, Taiwan
关键词
Detectors; Symbols; Computer architecture; MIMO communication; Indexes; Modulation; Iterative decoding; Spatial modulation; maximum a posteriori detection; log-likelihood ratio; maximum logarithm approximation; iterative detection and decoding; soft-input soft-output detection; MIMO DETECTION; DETECTION ALGORITHM; NEAR-CAPACITY; SIGNALS;
D O I
10.1109/TCSI.2022.3181629
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Soft-input soft-output (SISO) detector for the iterative detection and decoding of coded spatial modulation (SM) signals needs to compute the extrinsic bit log-likelihood ratio (LLR) associated with each detected bit. The maximum logarithmic maximum a posteriori (max-log-MAP) detector is known to perform closely to the optimal logarithmic maximum a posteriori (log-MAP) detector with much lower computational complexity. In this paper, we first apply several mathematical tricks to derive a new and low-complexity algorithm for the max-log-MAP detector. The proposed algorithm features a new tree pruning technique to visit few lattice points and a smart list administration technique to retain a max-log-MAP detector. By following the proposed algorithm, we then design a hardware architecture for SISO detection of coded SM signals over the scenario of 64-QAM symbols, 8 transmit antennas, and 4 receive antennas. Under the TSMC 40 nm CMOS technology, the VLSI implementation results reveal that our architecture requires 46.4K gates and leads to detection throughput 450 Mbps, while operating at clock frequency 400 MHz and consuming power 46 mW. Being the first hardware architecture for SISO detection of coded SM signals, our proposed low-cost max-log-MAP detector is very attractive.
引用
收藏
页码:3816 / 3828
页数:13
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