VLSI Implementation of a Real-time Modified Decision-based Algorithm for Impulse Noise Removal

In this paper, a Real-Time Impulse Noise Removal (RTINR) algorithm and its hardware architecture are proposed for denoising images corrupted with fixed valued impulse noise. A decision-based algorithm is modified in the proposed RTINR algorithm where the corrupted pixel is first detected & is restored with median or previous pixel value depending on the number of corrupted pixels in the image. The proposed RTINR architecture has been designed to reduce the hardware complexity as it requires 21 comparators, 4 adders, and 2 line buffers which in turn improve the execution time. The proposed architecture results better in qualitative and quantitative performance in comparison to different denoising schemes while evaluated based on PSNR, IEF, MSE, EKI, SSIM,& FOM. The proposed architecture has been simulated using the VIRTEX7 FPGA device and the reported maximum post place& route frequency is 360.88 MHz. The proposed RTINR architecture is capable of denoising images of size 512 x 512 at a frame rate of 686. The architecture has also been synthesized using UMC 90 nm technology where 103 mW power is consumed at a clock frequency of 100 MHz with a gate count of 23K (NAND2) including two memory buffers.