Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance

被引：38

作者：

Narasimhulu, K ^{[1
]}

Sharma, DK ^{[1
]}

Rao, VR ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2003年 / 50卷 / 12期

关键词：

Analog; CMOS optimization; lateral asymmetric channel (LAC); mixed signal CMOS; radio frequency (RF) CMOS; system on chip (SoC);

D O I：

10.1109/TED.2003.820120

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we have systematically investigated the effect of scaling on analog performance parameters in lateral asymmetric channel (LAC) MOSFETs and compared their performance with conventional (CON) MOSFETs for mixed-signal applications. Our results show that, in LAC MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, g(m)/I-D etc.) down to the 70-nm technology node, in addition to an improvement in drive current and other parameters over a wide range of channel lengths. A systematic comparison on the performance of amplifiers and CMOS inverters with CON and LAC MOSFETs is also performed. The tradeoff between power dissipation and device performance is explored with detailed circuit simulations for both CON and LAC MOSFETs.

引用

页码：2481 / 2489

页数：9

共 20 条

[1] Analog circuit performance and process scaling [J].

Annema, AJ .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1999, 46 (06) :711-725

[2]

[Anonymous], 2001, INT TECHNOLOGY ROADM

[3] Optimization and realization of sub-100-nm channel length single halo p-MOSFETs [J].

Borse, DG ;

Rani, M ;

Jha, NK ;

Chandorkar, AN ;

Vasi, J ;

Rao, VR ;

Cheng, B ;

Woo, JCS .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (06) :1077-1079

[4] Process outlook for analog and RF applications [J].

Bruines, JJP .

MICROELECTRONIC ENGINEERING, 2000, 54 (1-2) :35-48

[5]

Bult K., 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), P76, DOI 10.1109/ISSCC.1999.759110

[6]

BULT K, 2000, P ESS CIRC, P1

[7]

Buss D., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P423, DOI 10.1109/IEDM.1999.824184

[8]

CHENG B, 1999, VLSI S, P69

[9] Exploration of velocity overshoot in a high-performance deep sub-0.1-μm SOI MOSFET with asymmetric channel profile [J].

Cheng, BH ;

Rao, VR ;

Woo, JCS .

IEEE ELECTRON DEVICE LETTERS, 1999, 20 (10) :538-540

[10]

DESHPANDE HV, 2001, IEEE ELECT DEV LETT, V22

← 1 2 →