A Stacked Embedded DRAM Array for LPDDR4/4X using Hybrid Bonding 3D Integration with 34GB/s/1Gb 0.88pJ/b Logic-to-Memory Interface

被引:35
作者
Bai Fujun [1 ,4 ]
Jiang Xiping [1 ,5 ]
Wang Song [1 ,6 ]
Yu Bing [1 ]
Tan Jie [1 ]
Zuo Fengguo [1 ]
Wang Chunjuan [1 ]
Wang Fan [1 ]
Long Xiaodong [1 ]
Yu Guoqing [1 ]
Fu Ni [1 ]
Li Qiannan [1 ]
Li Hua [1 ]
Wang Kexin [1 ]
Duan Huifu [1 ]
Bai Liang [1 ]
Jia Xuerong [1 ]
Li Jin [1 ]
Li Mei [1 ]
Wang Zhengwen [1 ]
Hu Sheng [2 ]
Zhou Jun [2 ]
Zhan Qiong [2 ]
Sun Peng [2 ]
Yang Daohong [2 ]
Kau, Cheichan [2 ]
Yang, David [3 ]
Ho, Ching-Sung [3 ]
Sun Hongbin [4 ]
Lv Hangbing [5 ]
Liu Ming [5 ]
Kang Yi [6 ]
Ren Qiwei [1 ]
机构
[1] Xian UniIC Semicond Co Ltd, Xian, Shaanxi, Peoples R China
[2] Wuhan Xinxin Semicond Mfg Co Ltd, Wuhan, Hubei, Peoples R China
[3] Powerchip Semicond Mfg Corp, Hsinchu, Taiwan
[4] Xi An Jiao Tong Univ, Xian, Shaanxi, Peoples R China
[5] Chinese Acad Sci, Inst Microelect, Beijing, Peoples R China
[6] Univ Sci & Technol China, Hefei, Anhui, Peoples R China
来源
2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2020年
关键词
D O I
10.1109/IEDM13553.2020.9372039
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Increasing demand for DRAM scaling and high-bandwidth has driven DRAM technology to 3D/2.5D integration. With the innovative Hybrid Bonding technology, a new Stacked Embedded DRAM (SEDRAM) architecture was developed on LPDDR4/4X product. In this SEDRAM, a DRAM array wafer and logic wafer were fabricated separately and then face-to-face fusion connected through ultra-highdensity, low-resistance Hybrid Bonding. By separating the control, I/O, DFT and periphery circuits to a logic die, SEDRAM offers a novel approach to DRAM product development and accomplishes an extremely high-bandwidth logic-to-memory interface speed of 34GBps per 1Gb with low power consumption as low as 0.88pJ/bit.
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页数:4
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