Low noise and high photodetection probability SPAD in 180 nm standard CMOS technology

被引:10
|
作者
Accarino, Claudio [1 ]
Al-Rawhani, Mohammed [1 ]
Shah, Yash Diptesh [1 ]
Maneuski, Dzmitry [1 ]
Mitra, Srinjoy [1 ]
Buttar, Craig [1 ]
Cumming, David R. S. [1 ]
机构
[1] Univ Glasgow, Coll Sci & Engn, Glasgow, Lanark, Scotland
基金
英国工程与自然科学研究理事会;
关键词
single photon avalanche diode; SPAD; CMOS; low-light (vision); photo detector; image sensor; PHOTON AVALANCHE-DIODE;
D O I
10.1109/ISCAS.2018.8351173
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A square shaped, low noise and high photo-response single photon avalanche diode suitable for circuit integration, implemented in a standard CMOS 180 nm high voltage technology, is presented. In this work, a p+ to shallow n-well junction was engineered with a very smooth electric field profile guard ring to attain a photo detection probability peak higher than 50% with a median dark count rate lower than 2 Hz/mu m(2) when operated at an excess bias of 4 V. The reported timing jitter full width at half maximum is below 300 ps for 640 nm laser pulses.
引用
收藏
页数:4
相关论文
共 50 条
  • [41] A Low Power Low Noise VCO and a High Gain LNA for WSN in 130nm CMOS RF Technology
    Mukherjee, Arnov
    Rangaree, Pankaj H.
    Asutkar, Gajendra M.
    2015 INTERNATIONAL CONFERENCE ON SMART TECHNOLOGIES AND MANAGEMENT FOR COMPUTING, COMMUNICATION, CONTROLS, ENERGY AND MATERIALS (ICSTM), 2015, : 268 - 274
  • [42] A low noise vector modulator with integrated basebandfilter in 120 nm CMOS technology
    Simon, M
    Weigel, R
    2003 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2003, : 409 - 412
  • [43] A 260 GHz Low Phase Noise VCO in 40 nm CMOS Technology
    Zhou, Zhongliang
    Li, Qin
    2019 INTERNATIONAL CONFERENCE ON MICROWAVE AND MILLIMETER WAVE TECHNOLOGY (ICMMT 2019), 2019,
  • [44] Tunable Balun Low-Noise Amplifier in 65 nm CMOS Technology
    Sturm, Johannes
    Groinig, Marcus
    Xiang, Xinbo
    RADIOENGINEERING, 2014, 23 (01) : 319 - 327
  • [45] A fast and low noise charge sensitive preamplifier in 90 nm CMOS technology
    Baschirotto, A.
    Cocciolo, G.
    De Matteis, M.
    Giachero, A.
    Gotti, C.
    Maino, M.
    Pessina, G.
    JOURNAL OF INSTRUMENTATION, 2012, 7
  • [46] A low-noise current preamplifier in 120nm CMOS technology
    Uhrmann, H.
    Zimmermann, H.
    MIXDES 2007: Proceedings of the 14th International Conference on Mixed Design of Integrated Circuits and Systems:, 2007, : 199 - 202
  • [47] Cryogenic characterization of 180 nm CMOS technology at 100 mK
    Huang, R. G.
    Gnani, D.
    Grace, C.
    Kolomensky, Yu G.
    Mei, Y.
    Papadopoulou, A.
    JOURNAL OF INSTRUMENTATION, 2020, 15 (06)
  • [48] Clock generator IP design in 180 nm CMOS technology
    Meng, Xu
    Lin, Fujiang
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2016, 87 (03) : 369 - 377
  • [49] Clock generator IP design in 180 nm CMOS technology
    Xu Meng
    Fujiang Lin
    Analog Integrated Circuits and Signal Processing, 2016, 87 : 369 - 377
  • [50] Analogue multiplexer for neural application in 180 nm CMOS technology
    Zoladz, Miroslaw
    PRZEGLAD ELEKTROTECHNICZNY, 2010, 86 (11A): : 256 - 259