A power management unit with continuous co-locking of clock frequency and supply voltage for dynamic voltage and frequency scaling

被引:6
作者
Lee, Jeabin [1 ]
Nam, Byeong-Gya [1 ]
Song, Seong-Jun [1 ]
Cho, Namjun [1 ]
Yoo, Hoi-Jun [1 ]
机构
[1] Adv Inst Sci & Technol KAIST, Dept EECS, Taejon 305701, South Korea
来源
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年
关键词
D O I
10.1109/ISCAS.2007.378516
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
A power management unit (PMU) architecture is proposed for the domain-specific low power management with dynamic voltage and frequency scaling. The PMU continuously co-locks and dynamically varies the supply voltage and the clock frequency from 89 MHz to 200 MHz and from 1.0 V to 1.8 V, respectively, in less than 40 mu s. A 32bit RISC processor is used as power management target device. The PMU, 0.36mm(2) with 0.18-mu m CMOS process, consumes 5mW, and shows -100dBm/Hz phase noise of clock and 160mV load regulation of supply voltage with 100mA load current from the load, RISC processor.
引用
收藏
页码:2112 / 2115
页数:4
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