An Ultra Low Power, 10-bit Two-Step Flash ADC for Signal Processing Applications

An ultra low power, 10-bit two-step flash analog-to-digital converter (ADC) for communication and bio-potential signal processing applications is presented in this paper. In the proposed design the conventional open loop comparator is replaced with programmable bias inverter (PBI), the bias inverter (BI) consists of basic digital inverter with cascode PMOS and NMOS as bias transistors in the top and bottom. The switching threshold voltage of BI changes with different reference bias voltages, which compares the analog input voltage with BI switching threshold and provide respective digital outputs. The programmability of the BI makes the proposed ADC to operate from DC to 1 GS/s sampling frequency range and hence ADC power gets scaled accordingly. The major advantages of the PBI based two-step flash ADC is lower power consumption, smaller area and improved static/dynamic performance due to lower mismatch between the PBI comparators and smaller input capacitance. The proposed ADC is designed in 90nm standard CMOS process occupying a core area of 0.096 mm(2). The performance parameters of the proposed ADC are found to be, differential non-linearity (DNL) of +/- 0.38 LSB, integral non-linearity of +/- 0.54 LSB, signal-tonoise- and-distortion ratio (SNDR) of 57.38 dB, spurious free dynamic range (SFDR) of 69.3 dB, effective number of bits (ENOB) of 9.24 at 1.0 V supply voltage. The power consumption of this ADC at 100 kS/s sampling frequencies is 280 nW and at higher sampling frequencies upto 1 GS/s it is 5.6 mW.