Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded Into 40nm CMOS Logic Process for Automotive Microcontrollers

被引:0
|
作者
Luo, L. Q. [1 ,2 ]
Teo, Z. Q. [1 ]
Kong, Y. J. [1 ]
Deng, F. X. [1 ]
Liu, J. Q. [1 ]
Zhang, F. [1 ]
Cai, X. S. [1 ]
Tan, K. M. [1 ]
Lim, K. Y. [1 ]
Khoo, P.
Jung, S. M.
Siah, S. Y.
Shum, D. [1 ]
Pey, K. L. [2 ]
Shubhakar, K. [2 ]
Wang, C. M. [3 ]
Xing, J. C. [3 ]
Diao, Y. [3 ]
Lin, G. M. [3 ]
Tee, L. [3 ]
Lemke, S. M. [3 ]
Ghazavi, P. [3 ]
Liu, X. [3 ]
Do, N. [3 ]
机构
[1] GLOBALFOUNDRIES Singapore Pte Ltd, Singapore 738406, Singapore
[2] Singapore Univ Technol & Design, 8 Somapah Rd, Singapore 487372, Singapore
[3] Silicon Storage Technol Inc, San Jose, CA 95134 USA
来源
2016 IEEE 8TH INTERNATIONAL MEMORY WORKSHOP (IMW) | 2016年
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D O I
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中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
This paper for the first time successfully demonstrates a Logic-compatible, highly reliable, automotive-grade 16Mb flash macro with self-aligned, split-gate FG-based flash cell embedded into a 40nm Low Power CMOS with copper low K interconnects. Key Features of the flash macro: Dual power supply with operation temperature from-40 to 150 C; Random Read access lOns;d worst case condition; Low active and standby power; High raw endurance and data retention lifetime before using FCC. This technology provides large read current window which is compatible with both automotive MCU markets and low power mode tailored for smart card/industrial applications. The 16Mb Design test chip (DTC) with industry-leading cell size has demonstrated functionality with tight cell C, and read current distributions. The SO NVM cell and erase gate are processed with self alignment to gate spacer and polysilicon CMP (Chemical Mechanical Polishing) that can be easily integrated in a modular way to the standard logic process.
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页数:4
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