A G-Band on-off-Keying Low-Power Transmitter and Receiver for Interconnect Systems in 65-nm CMOS

This paper presents a G-band on-off-keying transmitter and a G-Band receiver in 65-nm bulk CMOS process. The proposed transmitter includes a high-efficiency push-push voltage-controlled oscillator (VCO) with body-bias and a switch-based modulator using the folded coupled-line topology. The benefits of the folded coupled-line in switch design are theoretically analyzed and proved. The receiver utilized a topology based on envelope detector and inverter-chain-based output buffer. The standalone VCO demonstrates a peak dc-RF efficiency of 4.1% at 209 GHz with 1.02 dBm output power. The switch-based modulator performs a minimum insertion loss of 1.6 dB with isolation better than 21 dB. The transmitter exhibits a maximum output power of -0.04 dBm at 208 GHz with 3% efficiency and a phase noise of -84.9 dBc at 1-MHz offset. The transmitter and receiver achieve 7.5-Gb/s errorless [bit error rate (BER) < 1 x 10(-12)] data rate with 1.73 pJ/b energy efficiency and 9 Gb/s with 1 x 10(-4) BER in loop-back test. The results of both the transmitter/receiver and standalone components show competitive performances at the frequency over 200 GHz among the designs in CMOS process.