Flexible Multi-Core Platform for a Multiple-Format Video Decoder

被引：3

作者：

Jo, Hyun-Ho ^{[1
]}

Ahn, Yong-Jo ^{[1
]}

Kang, Dae-Beom ^{[1
]}

Ji, Bongil ^{[1
]}

Sim, Dong-Gyu ^{[1
]}

Lee, Jae-Jin ^{[2
]}

机构：

[1] Kwangwoon Univ, Image Proc Syst Lab, Seoul 139701, South Korea

[2] Elect & Telecommun Res Inst, Multimedia Processor Res Sect, Taejon 305700, South Korea

来源：

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2015年 / 80卷 / 02期

关键词：

Multi-codec; Video decoder; ASIP; Multi-core platform; H.264; PARALLELIZATION; DESIGN;

D O I：

10.1007/s11265-013-0853-0

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a new multi-core platform that can decode various video compression formats including MPEG-2, MPEG-4, AVS, and H.264/AVC. The developed multi-core platform consists of multiple media cores that are designed based on an application-specific instruction-set processor (ASIP). To improve the decoding speed of each media core, we developed several designated instructions that are useful for decoding various video codecs. In addition, an inter-connected hardware structure and a new synchronization algorithm are proposed to reduce inter-core communication overheads and a shared memory contention on the multi-core platform. We achieved a speed-up of 2.2x in decoding video bitstreams using several designated instructions on the media core. Furthermore, we achieved a speed-up of 5.56x in decoding video bitstreams on the multi-core platform by employing macroblock-row level parallelism, compared with the developed media core without designated instructions. The developed multi-core platform was implemented on a Xilinx Virtex5 LX330 field-programmable gate array (FPGA) that operates at 60 MHz.

引用

页码：163 / 179

页数：17

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