Super-junction LDMOST on a silicon-on-sapphire substrate

被引：92

作者：

Nassif-Khalil, SG ^{[1
]}

Salama, CAT ^{[1
]}

机构：

[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2003年 / 50卷 / 05期

关键词：

insulating substrate; lateral; power MOSFET; super junction (SJ);

D O I：

10.1109/TED.2003.813460

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A super-junction lateral double diffused MOST (SJ-LDMOST) in silicon-on-sapphire technology, targeting power integrated circuits (PICs), is proposed, implemented and characterized. The proposed structure eliminates "substrate-assisted-depletion" effects in lateral SJ devices thus achieving charge compensation between the n and p SJ-pillars as well as a uniform electric field distribution in the drift region in the off-state. Three-dimensional (3-D) simulations of the device, using realistic aspect ratios for the SJ-pillars, indicate that a significant reduction in specific on-resistance for a given breakdown voltage can be achieved as compared to conventional reduced surface field (RESURF) devices. Experimental devices were implemented using a seven mask CMOS compatible. process. Fabricated SJ-LDMOSTs with a drift region length of 66 mum and a pillar aspect ratio of 1.2 mum/0.7 mum (width/height) exhibit a specific on-resistance of 0.82 Omega.cm(2) and a breakdown voltage (BV) ranging between 500 and 600 V corresponding to less than 8.5% charge imbalance in the pillars.

引用

页码：1385 / 1391

页数：7

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