Comparing controlled system synthesis and suppression enforcement

被引:4
作者
Aceto, Luca [1 ,2 ]
Cassar, Ian [2 ,3 ]
Francalanza, Adrian [3 ]
Ingolfsdottir, Anna [2 ]
机构
[1] Gran Sasso Sci Inst, Laquila, Italy
[2] Reykjavik Univ, Dept Comp Sci, Reykjavik, Iceland
[3] Univ Malta, Dept Comp Sci, Msida, Malta
基金
欧盟地平线“2020”;
关键词
Runtime enforcement; Controlled system synthesis; Modal mu-calculus; Process algebra;
D O I
10.1007/s10009-021-00624-0
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
Runtime enforcement and control system synthesis are two verification techniques that automate the process of transforming an erroneous system into a valid one. As both techniques can modify the behaviour of a system to prevent erroneous executions, they are both ideal for ensuring safety. In this paper, we investigate the interplay between these two techniques and identify control system synthesis as being the static counterpart to suppression-based runtime enforcement, in the context of safety properties.
引用
收藏
页码:601 / 614
页数:14
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