Packaged clock recovery integrated circuits for 40 GBit/s optical communication links

被引：6
|
作者：
Yu, R
Pierson, R
Zampardi, P
Runge, K
Campana, A
Meeker, D
Wang, KC
Petersen, A
Bowers, J
机构：
来源：
GAAS IC SYMPOSIUM - 18TH ANNUAL, TECHNICAL DIGEST 1996 | 1996年
关键词：
D O I：
10.1109/GAAS.1996.567824
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Three packaged clock recovery integrated circuits: a differentiate/rectify circuit, a delay/multiply circuit, and a phase detector circuit, were implemented in an advanced AlGaAs/GaAs HBT process. The packaged ICs show performance adequate for clock recovery for optical communication links of up to at least 40 GBit/s. With a 30 GBit/s pseudo-random sequence input, a phase-locked loop incorporating these ICs readily acquired and maintained phase lock, demonstrating the excellent system performance of these components.
引用
收藏
页码：129 / 132
页数：4
相关论文
共 50 条
  • [21] 40 Gbit/s demultiplexing experiment with 10 GHz all-optical clock recovery using a modelocked semiconductor laser
    Ludwig, R
    Ehrhardt, A
    Pieper, W
    Jahn, E
    Agrawal, N
    Ehrke, HJ
    Kuller, L
    Weber, HG
    ELECTRONICS LETTERS, 1996, 32 (04) : 327 - 329
  • [22] 40 Gbit/s all-optical clock recovery based on the injection mode-locked fiber ring laser
    Lv Jie
    Yu Jin-Long
    Wang Hong-Li
    Li Ya-Nan
    Yang En-Ze
    Optical and Quantum Electronics, 2007, 39 : 1145 - 1152
  • [23] Compact receiver module with integrated optical De-multiplexer for 40 Gbit/s and 100 Gbit/s
    Kawamura, Masanobu
    Nakajima, Fumihiro
    Oomori, Hiroyasu
    Hara, Hiroshi
    Yasaki, Atsushi
    SEI Technical Review, 2015, (80): : 66 - 70
  • [24] Compact and fully packaged wavelength converter with integrated delay loop for 40 Gbit/s RZ signals
    Leuthold, J
    Joyner, CH
    Mikkelsen, B
    Raybon, G
    Pleumeekers, JL
    Miller, BI
    Dreyer, K
    Burrus, CA
    OPTICAL AMPLIFIERS AND THEIR APPLICATIONS, PROCEEDINGS, 2002, 77 : 228 - 230
  • [25] 160-Gbit/s clock recovery using an electro-absorption modulator and 40-Gbit/s ETDM demultiplexer
    Taorong GONG
    Fengping YAN
    Dan LU
    Ming CHEN
    Peng LIU
    Peilin TAO
    Muguang WANG
    Tangjun LI
    Shuisheng JIAN
    Frontiers of Optoelectronics in China, 2009, 2 (04) : 389 - 392
  • [26] 160-Gbit/s clock recovery using an electro-absorption modulator and 40-Gbit/s ETDM demultiplexer
    Gong T.
    Yan F.
    Lu D.
    Chen M.
    Liu P.
    Tao P.
    Wang M.
    Li T.
    Jian S.
    Frontiers of Optoelectronics in China, 2009, 2 (4): : 389 - 392
  • [27] InP DHBT technology and design for 40 Gbit/s full-rate-clock communication
    Godin, J
    Riet, M
    Blayac, S
    Berdaguer, P
    Dhalluin, V
    Alexandre, F
    Kahn, M
    Pinquier, A
    Kasbari, A
    Moulu, J
    Konczykowska, A
    GAAS IC SYMPOSIUM - 24TH ANNUAL, TECHNICAL DIGEST 2002, 2002, : 215 - 218
  • [28] Design of half-rate clock and data recovery circuits for optical communication systems
    Savoj, J
    Razavi, B
    38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, 2001, : 121 - 126
  • [29] 56 Gbit/s analogue PLL for clock recovery
    Schwarz, V
    Willén, B
    Jäckel, H
    ELECTRONICS LETTERS, 2001, 37 (22) : 1336 - 1338
  • [30] Over 40-Gbit/s InPHEMT ICs for optical communication systems
    Suzuki, T
    Nakasha, Y
    Kano, H
    Sato, M
    Masuda, S
    Sawada, K
    Makiyama, K
    Takahashi, T
    Hirose, T
    Hara, N
    Takigawa, M
    IEICE TRANSACTIONS ON ELECTRONICS, 2003, E86C (10): : 1916 - 1922
12345