Packaged clock recovery integrated circuits for 40 GBit/s optical communication links

被引：6
|
作者：
Yu, R
Pierson, R
Zampardi, P
Runge, K
Campana, A
Meeker, D
Wang, KC
Petersen, A
Bowers, J
机构：
来源：
GAAS IC SYMPOSIUM - 18TH ANNUAL, TECHNICAL DIGEST 1996 | 1996年
关键词：
D O I：
10.1109/GAAS.1996.567824
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Three packaged clock recovery integrated circuits: a differentiate/rectify circuit, a delay/multiply circuit, and a phase detector circuit, were implemented in an advanced AlGaAs/GaAs HBT process. The packaged ICs show performance adequate for clock recovery for optical communication links of up to at least 40 GBit/s. With a 30 GBit/s pseudo-random sequence input, a phase-locked loop incorporating these ICs readily acquired and maintained phase lock, demonstrating the excellent system performance of these components.
引用
收藏
页码：129 / 132
页数：4
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