Performance optimization of GNRFET Inverter at 32nm technology node

Moore's law has been an important benchmark for developments in the field of microelectronics & information processing. In fact, it has played an instrumental role in driving the world economics and scaling down of the feature length has been the fundamental strategy for improving the performance of the device. However, as we continue to scale down, towards the nanometre regime, various factors like line edge roughness, tunnelling effects, random dopant fluctuations, short channel effects etc tends to effect it's functioning and thereupon, it's become of acute essence to investigate other alternative materials that could help extend the saturating Moore's Law. A lot of research is currently going in the area and many alternative technologies like CNFETs, FINFETs, GNRFETs etc. are being explored. Field-effect transistors using Graphene Nano-Ribbons (GNRFETs) have emerged as promising technology because of their excellent carrier transport properties and potential for large scale processing and fabrication. This paper explores the GNRFETs inverter performance with CMOS inverter at 32nm technology node. Simulations indicate about 2.5x improvements in the propagation delay and 2x improvements in the power delay product (PDP). Further optimization of results was obtained by varying the number of Nano-Ribbons along with the supply voltage. On varying the number of nano-ribbons it was found that, propagation delay decreases, while dynamic energy consumption increases. Based on the inference, the optimized result was chosen to be 15 nano-ribbon. The results indicate that that GNRFET is a promising alternative for Si-CMOS, making it an excellent proposition to help extend the saturating Moore's Law. (C) 2017 Elsevier Ltd. All rights reserved.