An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications

In a system on a chip (SoC), there are several long global wires that typically limit the maximum SoC clock speed. Therefore, through-silicon via (TSV) technology has been proposed to shorten the length of the global wires. However, the TSV delay variation phenomenon created during the manufacturing process may prevent SoC systems from working properly. This TSV delay variation problem affects data transmission between dies. In this paper, we present an all-digital delay-locked loop (ADDLL) architecture to synchronize clock signals between two dies. We implement the proposed ADDLL in TSMC 90-nm CMOS process with standard cells, which can tolerate process, voltage, and temperature (PVT) variations. In addition, the ADDLL architecture can overcome the TSV delay variation problem using only a single TSV channel. The proposed ADDLL can operate in an input frequency range of 195-960 MHz with a maximum phase error of less than 40.6 ps.