Contributions of channel gate and overlap gate currents on 1/f gate current noise for thin oxide gate p-MOSFETs

被引：0

作者：

Martinez, F ^{[1
]}

Laigle, A ^{[1
]}

Hoffmann, A ^{[1
]}

Valenza, M ^{[1
]}

Veloso, A ^{[1
]}

Jurczak, M ^{[1
]}

机构：

[1] Univ Montpellier 2, CNRS, UMR 5507, CEM2, F-34095 Montpellier, France

来源：

Noise and Fluctuations | 2005年 / 780卷

关键词：

MOSFETs; 1/f noise; tunneling; gate noise;

D O I：

暂无

中图分类号：

R318 [生物医学工程];

学科分类号：

0831 ;

摘要：

Dc Gate current and associated noise sources on a 90 nm CMOS technology are investigated. At high V-DS biases two do components are observed: one due to overlap, the second due to gate to channel tunneling. 1/f noise associated with these two components is studied. The presented results concern PMOST.

引用

页码：243 / 246

页数：4

共 3 条

[1] Noise modeling for RF CMOS circuit simulation
Scholten, AJ
Tiemeijer, LF
van Langevelde, R
Havens, RJ
Zegers-van Duijnhoven, ATA
Venezia, VC
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (03) : 618 - 632
[2] Impact of gate current noise on drain current noise in 90 nm CMOS technology
Valenza, M
Laigle, A
Martinez, F
Hoffmann, A
Rigaud, D
[J]. ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, : 287 - 290
[3] VELOSO A, 2002, P ESSDERC 2002 FIR I, P159

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