Increasing the noise margin in organic circuits using dual gate field-effect transistors

被引：61

作者：

Spijkman, M. ^{[1
]}

Smits, E. C. P. ^{[1
]}

Blom, P. W. M. ^{[1
]}

de Leeuw, D. M. ^{[1
]}

Saint Come, Y. Bon ^{[2
]}

Setayesh, S. ^{[2
]}

Cantatore, E. ^{[3
]}

机构：

[1] Univ Groningen, Zernike Inst Adv Mat, NL-9747 AG Groningen, Netherlands

[2] Philips Res Labs, NL-5656 AE Eindhoven, Netherlands

[3] Eindhoven Univ Technol, Dept Elect Engn, NL-5600 MB Eindhoven, Netherlands

来源：

APPLIED PHYSICS LETTERS | 2008年 / 92卷 / 14期

关键词：

Capacitance - Electric inverters - Field effect transistors - Logic gates - Phase noise - Threshold voltage;

D O I：

10.1063/1.2904624

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Complex digital circuits reliably work when the noise margin of the logic gates is sufficiently high. For p-type only inverters, the noise margin is typically about 1 V. To increase the noise margin, we fabricated inverters with dual gate transistors. The top gate is advantageously used to independently tune the threshold voltage. The shift can be quantitatively described by Delta V-th=(C-t/C-b)V-top gate, where C-t and C-b are the top and bottom gate capacitances. We show that by adjusting the top gate biases, the noise margin of dual gate inverters can be significantly improved up to about 5 V. (C) 2008 American Institute of Physics.

引用

页数：3

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