Efficient Reconfigurable Vandermonde Matrix Inverter for Erasure-Correcting Generalized Integrated Interleaved Decoding

Generalized integrated interleaved (GII) codes constructed using Reed-Solomon (RS) codes enable local erasure correction with low complexity and are essential to shorten the failure recovery latency in hyper-scale distributed storage. Erasure corrections for storage systems are usually done by multiplying the inverse of a Vandermonde matrix to the syndrome vector. Previous Vandermonde matrix inversion architectures suffer from long latency. Besides, the GII decoding rounds have increasing erasure-correcting capability. Using a Vandermonde inverter dedicated for worst-case erasure correction leads to low hardware efficiency. This paper first proposes a low-latency Vandermonde matrix inverter architecture. By exploiting the regularity of our proposed architecture, an efficient re-configurable inverter supporting matrices of variable sizes is also developed to increase the efficiency of GII-RS erasure-correcting decoding. For 8 x 8 matrix inversion over GF(2(8)), our proposed architecture reduces the latency by 77% with similar complexity compared to the previous design. Our reconfigurable inverter for an example GII code achieves 64% and 32% reductions on latency and area, respectively, compared to the best alternative design.