A CMOS Time-to-digital converter for multi-voltage threshold method in Positron Emission Tomography

Avoiding use of traditional high-speed analog-to digital converters (ADCs) and constant fraction discriminators, multi-voltage threshold (MVT) method is able to digitally sample positron emission tomography (PET) scintillation pulse with reasonable cost. As the key component of the MVT method, a time-to-digital convertor (TDC) with high resolution and large dynamic range is presented in this work. The TDC architecture uses a delay locked loop (DLL) to generate the fast clock edges from a 100 MHz clock, and a 32-stage Vernier delay lines (VDL) is used to achieve the 40pS timing resolution. The proposed TDC is designed using the standard 0.25 mu m CMOS technology with 2.5V normal supply voltage. The power consumption of the TDC is similar to 70 mW.