Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction

In this paper, we present several optimization techniques for pourer reduction utilizing circuit symmetries. There are four kinds of symmetries that we detect in a given circuit implementation. First, we propose an algorithm for detecting the four different types of symmetries in a given circuit implementation of a Boolean function. Several re-synthesis techniques utilizing such symmetries are proposed. These techniques enable vs to optimize pourer consumption and delay with no (or very little) area overhead. We have carried out experiments on MCNC benchmark circuits to demonstrate the efficiency of the proposed techniques. The average power reduction in 14% with little or none area and/or delay overhead.