A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors

被引：11

作者：

Yasin, Ahmad ^{[1
,2
,6
]}

Haj-Yahya, Jawad ^{[3
,7
]}

Ben-Asher, Yosi ^{[4
]}

Mendelson, Avi ^{[5
]}

机构：

[1] Univ Haifa, Haifa, Israel

[2] Intel Corp, Santa Clara, CA 95051 USA

[3] Swiss Fed Inst Technol, Zurich, Switzerland

[4] Univ Haifa, Dept Comp Sci, IL-3498838 Haifa, Israel

[5] Technion, CS Dept, IL-320003 Haifa, Israel

[6] POB 1997, IL-1790700 Kafr Manda, Israel

[7] CAB F 72,Univ Str 6, CH-8092 Zurich, Switzerland

来源：

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION | 2019年 / 16卷 / 04期

关键词：

Performance analysis; performance comparison; benchmarking; microarchitecture; instruction set architecture; compiler code generation; PERFORMANCE; TOOLS;

D O I：

10.1145/3369383

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The slowdown in technology scaling puts architectural features at the forefront of the innovation in modern processors. This article presents a Metric-Guided Method (MGM) that extends Top-Down analysis with carefully selected, dynamically adapted metrics in a structured approach. Using MGM, we conduct two evaluations at the microarchitecture and the Instruction Set Architecture (ISA) levels. Our results show that simple optimizations, such as improved representation of CISC instructions, broadly improve performance, while changes in the Floating-Point execution units had mixed impact. Overall, we report 10 architectural insights at the microarchitecture, ISA, and compiler fronts while quantifying their impact on the SPEC CPU benchmarks.

引用

页数：25

共 39 条

[11]

Gwennap L., 2017, MICROPROCESSOR REPOR, V4

[12]

Haj-Yihia J., 2015, HIPC

[13] Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems [J].

Haj-Yihia, Jawad ;

Yasin, Ahmad ;

Ben Asher, Yosi ;

Mendelson, Avi .

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2016, 13 (04)

[14] HASWELL: THE FOURTH-GENERATION INTEL CORE PROCESSOR [J].

Hammarlund, Per ;

Martinez, Alberto J. ;

Bajwa, Atiq A. ;

Hill, David L. ;

Hallnor, Erik ;

Jiang, Hong ;

Dixon, Martin ;

Derr, Michael ;

Hunsaker, Mikal ;

Kumar, Rajesh ;

Osborne, Randy B. ;

Rajwar, Ravi ;

Singhal, Ronak ;

D'Sa, Reynold ;

Chappell, Robert ;

Kaushik, Shiv ;

Chennupaty, Srinivas ;

Jourdan, Stephan ;

Gunther, Steve ;

Piazza, Tom ;

Burton, Ted .

IEEE MICRO, 2014, 34 (02) :6-20

[15]

Heirman W, 2011, I S WORKL CHAR PROC, P38, DOI 10.1109/IISWC.2011.6114195

[16]

Jaleel Aamer, 2010, Memory characterization of workloads using instrumentation-driven simulation

[17]

Kanev S., 2016, ACM SIGARCH Computer Architecture News, V43, P158

[18]

Liu X., 2015, P INT C HIGH PERF CO, P1

[19] Pin: Building customized program analysis tools with dynamic instrumentation [J].

Luk, CK ;

Cohn, R ;

Muth, R ;

Patil, H ;

Klauser, A ;

Lowney, G ;

Wallace, S ;

Reddi, VJ ;

Hazelwood, K .

ACM SIGPLAN NOTICES, 2005, 40 (06) :190-200

[20]

McKenney PE, 1999, SOFTWARE PRACT EXPER, V29, P219, DOI 10.1002/(SICI)1097-024X(199903)29:3<219::AID-SPE230>3.0.CO

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