A hardware/software co-design approach for face recognition

被引:0
作者
Li, XG [1 ]
Areibi, S [1 ]
机构
[1] Univ Guelph, Sch Engn, Guelph, ON N1G 2W1, Canada
来源
16TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, PROCEEDINGS | 2004年
关键词
ANN; face recognition; FPGA; H/S co-design;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Face recognition is a technique employed in large-scale citizen identification applications, surveillance applications, law enforcement applications such as booking stations, and kiosks. Artificial Neural Networks (ANNs) have been proved to be all effective way to solve this problem, but due to the long-time training process, this approach can Hot be implemented efficiently by software. Although, hardware implementations can speedup the training process, this may lead to an inflexible solution. To balance flexibility (i.e. software implementations) and performance (i.e. hardware implementations), an embedded computing system consisting of both a processor and dedicated hardware on a Field Programmable Gate Array (FPGA) chip is proposed to solve face recognition based on all ANN approach. Results obtained indicate that this system achieves almost twice the speedup over a pure software implementation.
引用
收藏
页码:55 / 58
页数:4
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