High-level test synthesis for behavioral and structural designs

被引：3
作者：
Papachristou, CA [1 ]
Baklashov, M
Lai, K
机构：
[1] Case Western Reserve Univ, Dept Comp Engn, Cleveland, OH 44106 USA
[2] Synopsys Inc, Mountain View, CA 94043 USA
[3] Rockwell Semicond Syst, Newport Beach, CA 92660 USA
来源：
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 1998年 / 13卷 / 02期
关键词：
test synthesis; built-in self test; DFT;
D O I：
10.1023/A:1008309921888
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
High-Level Test Synthesis (HLTS), a term introduced in recent years, promises automatic enhancement of testability of a circuit. In this paper we will show how HLTS can achieve higher testability for BIST-oriented test methodologies. Our results show considering testability during high-level synthesis, better testability can be obtained when compared to DFT at low level. Transformation for testability, which allows behavioral modification for testability, is a very powerful HLTS technique.
引用
收藏
页码：167 / 188
页数：22
相关论文
共 24 条
[11]  
Gentil M. H., 1994, Proceedings 12th IEEE VLSI Test Symposium (Cat. No.94TH0645-2), P421, DOI 10.1109/VTEST.1994.292279
[12]  
HARMANANI H, 1993, P INT C COMP AID DES, P30
[13]  
HARRIS IG, 1994, PR IEEE COMP DESIGN, P101, DOI 10.1109/ICCD.1994.331864
[14]   BIST testability enhancement of system-level circuits: Experience with an industrial design [J].
Lai, KW ;
Papachristou, CA .
PROCEEDINGS OF THE FIFTH ASIAN TEST SYMPOSIUM (ATS '96), 1996, :219-224
[15]  
LEE TC, 1993, P DES AUT C, P292
[16]  
MAJUMDAR A, 1994, J ELECTRON TEST, V5, P43
[17]  
Papachristou C, 1995, PROCEEDINGS - INTERNATIONAL TEST CONFERENCE 1995, P693, DOI 10.1109/TEST.1995.529899
[18]  
PAPACHRISTOU CA, 1991, P 28 DES AUT C, P378
[19]  
PARULKAR I, 1995, P DES AUT C, P395
[20]   AUTOMATED TRANSFORMATION OF ALGORITHMS INTO REGISTER-TRANSFER LEVEL IMPLEMENTATIONS [J].
PENG, Z ;
KUCHCINSKI, K .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13 (02) :150-166
123