High-level test synthesis for behavioral and structural designs

被引：3

作者：

Papachristou, CA ^{[1
]}

Baklashov, M

Lai, K

机构：

[1] Case Western Reserve Univ, Dept Comp Engn, Cleveland, OH 44106 USA

[2] Synopsys Inc, Mountain View, CA 94043 USA

[3] Rockwell Semicond Syst, Newport Beach, CA 92660 USA

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 1998年 / 13卷 / 02期

关键词：

test synthesis; built-in self test; DFT;

D O I：

10.1023/A:1008309921888

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

High-Level Test Synthesis (HLTS), a term introduced in recent years, promises automatic enhancement of testability of a circuit. In this paper we will show how HLTS can achieve higher testability for BIST-oriented test methodologies. Our results show considering testability during high-level synthesis, better testability can be obtained when compared to DFT at low level. Transformation for testability, which allows behavioral modification for testability, is a very powerful HLTS technique.

引用

页码：167 / 188

页数：22

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