Approximate Conditional Carry Adder for Error Tolerant Applications

被引:0
|
作者
Roy, Avishek Sinha [1 ]
Prasad, N. [1 ]
Dhar, Anindya Sundar [1 ]
机构
[1] Indian Inst Technol, Dept Elect & Elect Commun Engn, Kharagpur 721302, W Bengal, India
关键词
Approximate adder; conditional carry; conditional sum; energy- and power-delay product; reliability;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Conditional carry adder has the advantage of best delay characteristics compared to other fast adders. This article presents approximate models of conditional carry adder (CCA), suitable in considering for error tolerant applications. Four approximate models (Approx1, Approx2, Approx3, and Approx4) with different levels of approximation have been proposed, which can be extended further to an n-level approximate model. Bit probabilities at outputs of the internal gates have been considered in deducing the approximate models of the circuit. Exclusive analysis has been done for an 8-bit conditional carry adder, whose deductions can be considered for the adder of any size. Implementation results on ASIC platform have shown an improvement of 15.833% and 14.256% in terms of area and operating speed, and 20.228% and 38.918% in terms of power-delay product and energy-delay product, when compared with exact CCA, respectively.
引用
收藏
页数:6
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