A Design of Charge Pump for Low Noise Phase-Locked Loops using Clock Quadrature

被引：1

作者：

Kim, Min Yeong ^{[1
]}

Lee, Kang Yoon ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Dept Elect & Comp Engn, Suwon, South Korea

来源：

2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020) | 2020年

关键词：

Low Noise; Wide Bandwidth; PhaseLocked-Loops; Clock Quadrature; Differential Charge Pump;

D O I：

10.1109/ISOCC50952.2020.9333003

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes A Design of charge pump for fast rising and falling time and adequate for Sigma Delta Modulation (SDM). Low Noise Phase-Locked Loop (PLL) architecture using reference clock quadrature is shown. The degree of noise performance improvement that can be obtained using clock quadrature is expressed in an expression. To fulfill the speed of the quadrupled reference clock, fully differential charge pump (CP) architecture is used. Also, Implemented the design of a unity gain buffer in charge pump for the optimized operation for Sigma Delta Modulation (SDM) which is also adequate for wide bandwidth PLL because of the high bandwidth and the ability to handle high load current. The proposed structure is implemented using CMOS 40nm process and uses 1.1V supply power.

引用

页码：262 / 263

页数：2