Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input

This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 mu A for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 mu s. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage.