Impact of gate-leakage currents on CMOS circuit performance

被引：6

作者：

Marras, A ^{[1
]}

De Munari, I ^{[1
]}

Vescovi, D ^{[1
]}

Ciampolini, P ^{[1
]}

机构：

[1] Univ Parma, Dipartamento Ingn Informaz, I-43100 Parma, Italy

来源：

MICROELECTRONICS RELIABILITY | 2005年 / 45卷 / 3-4期

关键词：

D O I：

10.1016/j.microrel.2004.09.006

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Ultra-thin gate dielectrics are exploited in fabrication of MOSFETs featuring channel lengths in the decananometer range: according to the ITRS oxide thickness in the order of 1 nm will be used in 2005 for ultra-short channel CMOS. For such aggressively scaled devices, gate-leakage currents represent a critical issue. In this paper, a study on the impact of direct-tunneling (DT) current on the performance of a wide variety of CMOS circuits is presented. The approach relies on a mixed-mode simulation approach, which allows for predicting the correlation of major performance indices with oxide thickness. (C) 2004 Elsevier Ltd. All rights reserved.

引用

页码：499 / 506

页数：8

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