New Scaling Limitation of the Floating Gate Cell in NAND Flash Memory

被引：32

作者：

Kim, Yong Seok ^{[1
]}

Lee, Dong Jun ^{[1
]}

Lee, Chi Kyoung ^{[1
]}

Choi, Hyun Ki ^{[1
]}

Kim, Seong Soo ^{[1
]}

Song, Jai Hyuk ^{[1
]}

Song, Du Heon ^{[1
]}

Choi, Jeong-Hyuk ^{[1
]}

Suh, Kang-Deog ^{[2
]}

Chung, Chilhee ^{[1
]}

机构：

[1] Samsung Elect Co, Semicond Business Div, NAND Flash Proc Architecture Team, San 24, Yongin 446711, Gyunggi Do, South Korea

[2] Sungkyunkwan Univ, Sch Informat & Commun Engn, Suwon 440746, South Korea

来源：

2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | 2010年

关键词：

Scaling Limitation; interference; Floating Gate Type NAND Flash;

D O I：

10.1109/IRPS.2010.5488765

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As the scaling in NAND Flash Memory is progressed, the various interferences among the adjacent cells are more and more increased and the new phenomenon which is ignored until now has to be considered. In this paper, we will introduce the new program interference phenomenon which is generated between the program word line and the adjacent word lines along the bit-line. This new program interference is that the Vth's of the adjacent word lines along the bit-line are decreased while a word line is programming. Because this phenomenon is severely aggravated as the gate space is decreased, we have to consider this program interference for the future technology nodes.

引用

页码：599 / 603

页数：5

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