A 10-b 120-MS/s 45 nm CMOS ADC using a re-configurable three-stage switched amplifier

A 10-b 120-MS/s pipeline analog-to-digital converter (ADC) is implemented in a 45 nm CMOS process. Three-stage amplifiers based on reversed nested Miller compensation and Multipath zero cancellation techniques are employed in the input sample-and-hold amplifier (SHA) and two multiplying digital-to-analog converters (MDACs). A single re-configurable three-stage switched amplifier is shared between two adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs. A charge redistributed input sampling network properly handles both single-ended and differential SHA inputs with a swing range of 1.2 Vpp around a 1.6 V common-mode voltage. The prototype ADC with an active die area of 0.58 mm(2) consumes 61.6 mW at 120 MS/s and 1.1 V. The measured differential and integral nonlinearities are within +/- 0.44 and +/- 0.75 LSB, respectively. At a sampling rate of 120 MHz with a 4.2 MHz sinusoidal input, the measured maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range are 55.6 and 70.4 dB, respectively.