Performance Degradation Monitoring for Analog Circuits Using Lightweight Built-in Components

被引:4
作者
Bilgic, Bora [1 ]
Ozev, Sule [1 ]
机构
[1] Arizona State Univ, Sch Elect Comp & Energy Engn, Tempe, AZ 85281 USA
来源
2022 IEEE 40TH VLSI TEST SYMPOSIUM (VTS) | 2022年
基金
美国国家科学基金会;
关键词
performance; locking; degradation; monitoring; analog; low drop out; security; detection; ELMORE DELAY; SELF-TEST; MODEL; PLL;
D O I
10.1109/VTS52500.2021.9794141
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The need for digital calibration due to large variations in fine-geometry processes as well as the need for performance locking mechanisms to prevent IC piracy have resulted in the prevalent use of digital assistance for analog circuits. The same issues also make analog circuits vulnerable to infield performance degradation either due to wearout or due to potential attacks by adversaries. Unfortunately, most of the vulnerabilities are activated after the device is deployed. In order to ensure secure and reliable operation of the system, abrupt performance fluctuations in analog circuits need to be detected in the field. The detection method needs to be robust with respect to process variations, low-cost, and avoid providing information that attackers can use to compromise the circuit. In this paper, we propose a simple method for detecting performance degradation of digitally-assisted analog circuits using simple circuit elements, such as level shifters and inverters. The proposed method identifies an easy-to-monitor invariant in the circuit that is correlated to performance variables but this correlation is not known to attackers. The proposed method is demonstrated on a low drop out voltage regulator (LDO). Experimental results confirm that the proposed method can detect deviations in performance due to the alteration of calibration or performance locking bits.
引用
收藏
页数:7
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