PySyn: A Rapid Synthesis for Mixed-Signal Machine Learning Classification

被引:1
作者
Kenarangi, Farid [1 ]
Partin-Vaisband, Inna [1 ]
机构
[1] Univ Illinois, Dept Elect & Comp Engn, Chicago, IL 60607 USA
来源
2021 IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2021年
关键词
mixed-signal; machine learning; classification; synthesis; ANALOG;
D O I
10.1109/MWSCAS47672.2021.9531745
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Mixed-signal integrated circuits (ICs) for machine learning (ML) have been demonstrated as a powerful tool for efficient and accurate classification of large volumes of complex data. Despite the growing interest in ML ICs, the design process of mixed-signal ML classifiers is dominated by ad hoc approaches. In this paper, a rapid synthesizer is developed in Python (PySyn) for designing compact power-efficient high-performance ML classifiers. Circuit-level ML library is designed and leveraged within the flow. System-level tradeoffs are generated with PySyn and utilized to iteratively adjust the ML performance. PySyn is demonstrated with a state-of-the-art classifier, generating optimized netlists under input constraints.
引用
收藏
页码:712 / 717
页数:6
相关论文
共 17 条
[1]  
Aly M., 2005, Neural Netw, V19, P2
[2]  
Bankman D, 2018, ISSCC DIG TECH PAP I, P222, DOI 10.1109/ISSCC.2018.8310264
[3]   Synthesis Procedure of Configurable Building Block-Based Linear and Nonlinear Analog Circuits [J].
Bhanja, Mousumi ;
Ray, Baidya Nath .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 36 (12) :1940-1953
[4]   A survey on feature selection methods [J].
Chandrashekar, Girish ;
Sahin, Ferat .
COMPUTERS & ELECTRICAL ENGINEERING, 2014, 40 (01) :16-28
[5]   Computer-aided design of analog and mixed-signal integrated circuits [J].
Gielen, GGE ;
Rutenbar, RA .
PROCEEDINGS OF THE IEEE, 2000, 88 (12) :1825-1852
[6]   A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training [J].
Gonugondla, Sujan K. ;
Kang, Mingu ;
Shanbhag, Naresh R. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (11) :3163-3173
[7]  
Kenarangi, 2019, ARXIV PREPRINT ARXIV
[8]   Leveraging Independent Double-Gate FinFET Devices for Machine Learning Classification [J].
Kenarangi, Farid ;
Partin-Vaisband, Inna .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66 (11) :4356-4367
[9]   Synthesis of Active Cell Balancing Architectures for Battery Packs [J].
Lukasiewycz, Martin ;
Kauer, Matthias ;
Steinhorst, Sebastian .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (11) :1876-1889
[10]   FEATS: Framework for Explorative Analog Topology Synthesis [J].
Meissner, Markus ;
Hedrich, Lars .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (02) :213-226