An integer cosine transform chip design for image compression

被引：3

作者：

Ruiz, GA ^{[1
]}

Michell, JA ^{[1
]}

Burón, AM ^{[1
]}

Solana, JM ^{[1
]}

Manzano, MA ^{[1
]}

Díaz, J ^{[1
]}

机构：

[1] Univ Cantabria, Fac Ciencias, Dept Elect & Comp, E-39005 Santander, Spain

来源：

VLSI CIRCUITS AND SYSTEMS | 2003年 / 5117卷

关键词：

integer cosine transform; multiplication free DCT; discrete cosine transform; image compression; parallel pipelined architectures; VLSI;

D O I：

10.1117/12.498771

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The Integer Cosine Transform (ICT) has been shown to be an alternative to the Discrete Cosine Transform (DCT) for image processing. This paper presents a parallel-pipelined architecture of an 8x8 ICT(10, 9, 6, 2, 3, 1) processor for image compression. The main characteristics of this architecture are: high throughput, low latency, reduced internal storage and 100% efficiency in all computational elements. The processor has been designed in 0.35-mum CMOS technology with an estimated operational frequency of 300MHz.

引用

页码：33 / 41

页数：9

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