A re-evaluation of the practicality of floating-point operations on FPGAs

被引：41

作者：

Ligon, WB ^{[1
]}

McMillan, S ^{[1
]}

Monn, G ^{[1
]}

Schoonover, K ^{[1
]}

Stivers, F ^{[1
]}

Underwood, KD ^{[1
]}

机构：

[1] Clemson Univ, Dept Elect & Comp Engn, Planet Earth Res Lab, Clemson, SC 29634 USA

来源：

IEEE SYMPOSIUM ON FPGAS FOR CUSTOM COMPUTING MACHINES, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/FPGA.1998.707898

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The use of reconfigurable hardware to perform high precision operations such as IEEE floating point operations has been limited in the past by FPGA resources. We discuss the implementation of IEEE single precision floating-point multiplication and addition. Then, we assess the practical implications of using these operations in the Xilinx 4000 series FPGAs considering densities available now and scheduled for the near future. For each operation, me present space requirements and performance information. This is followed by a discussion of an algorithm, matrix: multiplication , based on these operations, which achieves performance comparable to conventional microprocessors. Algorithm implementation options and their performance implications are discussed and corresponding measured results are given.

引用

页码：206 / 215

页数：10