High-Linearity Self-Biased CMOS Current Buffer

被引：1

作者：

Alejandro Martinez-Nieto, Javier ^{[1
]}

Teresa Sanz-Pascual, Maria ^{[1
]}

Medrano-Marques, Nicolas ^{[2
]}

Calvo-Lopez, Belen ^{[2
]}

Sarmiento-Reyes, Arturo ^{[1
]}

机构：

[1] Natl Inst Astrophys Opt & Elect INAOE, Dept Elect, Puebla 72840, Mexico

[2] Univ Zaragoza, Grp Elect Design GDE, E-50009 Zaragoza, Spain

来源：

ELECTRONICS | 2018年 / 7卷 / 12期

关键词：

class AB operation; CMOS; current mirror; current buffer; quasi floating gate; low power; AB CURRENT MIRRORS; POWER; OTA; AMPLIFIER;

D O I：

10.3390/electronics7120423

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A highly linear fully self-biased class AB current buffer designed in a standard 0.18 mu m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 mu W, features an input resistance as low as 89 Omega, high accuracy in the input-output current ratio and total harmonic distortion (THD) figures lower than -60 dB at 30 mu A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications.

引用

页数：18

共 50 条

[31] Design and implementation of a miniaturized high-linearity 3-5 GHz ultrawideband CMOS lownoise amplifier [J].

Lin, Yo-Sheng ;

Yang, Zheng-Hua ;

Chen, Chi- Chen ;

Chao, Tai-Cheng .

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2007, 49 (03) :524-526

[32] A 12-bit 2.32 GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer [J].

Guo, Xuehao ;

Li, Zhiyang ;

Fang, Hao ;

Jia, Zelin ;

Tian, Fuli ;

Song, Chunyi ;

Xu, Zhiwei .

IEICE ELECTRONICS EXPRESS, 2023, 20 (23)

[33] Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers [J].

Grasso, Alfio Dario ;

Marano, Davide ;

Esparza-Alfaro, Fermin ;

Lopez-Martin, Antonio J. ;

Palumbo, Gaetano ;

Pennisi, Salvatore .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (03) :663-670

[34] A 0.1-20 GHz Low-Power Self-Biased Resistive-Feedback LNA in 90 nm Digital CMOS [J].

Chen, Mingqi ;

Lin, Jenshan .

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2009, 19 (05) :323-325

[35] A Calibration Scheme for Stability of Self-biased Ring Amplifier [J].

Yan, Rongshen ;

Chan, Chi-Hang ;

Sin, Sai-Weng ;

Seng-Pan, U. ;

Martins, R. P. .

2017 6TH INTERNATIONAL CONFERENCE ON ADVANCED MATERIALS AND COMPUTER SCIENCE (ICAMCS 2017), 2017, :226-235

[36] Self-Biased 0.13-μm CMOS 2.4-GHz Class E Cascode Power Amplifier [J].

Fouad, Hafez ;

Zekry, Abdel-halim ;

Fawzy, Khalid .

NRSC: 2009 NATIONAL RADIO SCIENCE CONFERENCE: NRSC 2009, VOLS 1 AND 2, 2009, :770-781

[37] A self-biased PLL with low power and compact area [J].

贾海珑 ;

陈先敏 ;

刘琦 ;

冯光涛 .

Journal of Semiconductors, 2015, (10) :132-136

[38] A self-biased PLL with low power and compact area [J].

Jia, Hailong ;

Chen, Xianmin ;

Liu, Qi ;

Feng, Guangtao .

JOURNAL OF SEMICONDUCTORS, 2015, 36 (10)

[39] A DOUBLE-DIFFERENTIAL-INPUT / DIFFERENTIAL-OUTPUT FULLY COMPLEMENTARY AND SELF-BIASED ASYNCHRONOUS CMOS COMPARATOR [J].

Milovanovic, Vladimir ;

Zimmermann, Horst .

FACTA UNIVERSITATIS-SERIES ELECTRONICS AND ENERGETICS, 2014, 27 (04) :649-662

[40] A 137-GHz Ultra-Wide Bandwidth High-Linearity CMOS Distributed Amplifier for High-Speed Communication [J].

Lee, Dongwon ;

Park, Jeongsoo ;

Choi, Kyung-Sik ;

Liu, Yuqi ;

Wang, Hua .

IEEE 49TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE, ESSCIRC 2023, 2023, :73-76

← 1 2 3 4 5 →