High-Linearity Self-Biased CMOS Current Buffer

被引：1

作者：

Alejandro Martinez-Nieto, Javier ^{[1
]}

Teresa Sanz-Pascual, Maria ^{[1
]}

Medrano-Marques, Nicolas ^{[2
]}

Calvo-Lopez, Belen ^{[2
]}

Sarmiento-Reyes, Arturo ^{[1
]}

机构：

[1] Natl Inst Astrophys Opt & Elect INAOE, Dept Elect, Puebla 72840, Mexico

[2] Univ Zaragoza, Grp Elect Design GDE, E-50009 Zaragoza, Spain

来源：

ELECTRONICS | 2018年 / 7卷 / 12期

关键词：

class AB operation; CMOS; current mirror; current buffer; quasi floating gate; low power; AB CURRENT MIRRORS; POWER; OTA; AMPLIFIER;

D O I：

10.3390/electronics7120423

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A highly linear fully self-biased class AB current buffer designed in a standard 0.18 mu m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 mu W, features an input resistance as low as 89 Omega, high accuracy in the input-output current ratio and total harmonic distortion (THD) figures lower than -60 dB at 30 mu A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications.

引用

页数：18

共 50 条

[21] Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage [J].

Avaneesh K. Dubey ;

R. K. Nagaria .

Analog Integrated Circuits and Signal Processing, 2019, 101 :307-317

[22] Design of a low voltage low power self-biased OTA using independent gate FinFET and PTM models [J].

Shirazi, Mandi ;

Hassanzadeh, Alireza .

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2017, 82 :136-144

[23] Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage [J].

Dubey, Avaneesh K. ;

Nagaria, R. K. .

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2019, 101 (02) :307-317

[24] CMOS Bandgap References With Self-Biased Symmetrically Matched Current-Voltage Mirror and Extension of Sub-1-V Design [J].

Lam, Yat-Hei ;

Ki, Wing-Hung .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 18 (06) :857-865

[25] A High-Linearity Fully-Differential Mixer [J].

Li, X. B. ;

Zhao, M. J. ;

Wu, Z. H. ;

Li, B. .

2011 INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2011,

[26] Low-Noise and High-Linearity Wideband CMOS Receiver Front-End Stacked With Glass Integrated Passive Devices [J].

Ye, Rong-Fu ;

Horng, Tzyy-Sheng ;

Wu, Jian-Ming .

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2014, 62 (05) :1229-1238

[27] A Self-Biased Subthreshold CMOS Voltage Reference With Temperature Compensation Circuit for IoT Self-powered Sensor Applications [J].

Huang, Yuxuan ;

Yan, Feng ;

Sun, Kangkang ;

Liu, Jingjing .

2023 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS, 2024, :134-138

[28] Complementary self-biased logics based on single-electron transistor (SET)/CMOS hybrid process [J].

Song, KW ;

Lee, YK ;

Sim, JS ;

Kim, KR ;

Lee, JD ;

Park, BG ;

You, YS ;

Park, JO ;

Jin, YS ;

Kim, YW .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2005, 44 (4B) :2618-2622

[29] Design of a K-Band High-Linearity Asymmetric SPDT CMOS Switch Using a Stacked Transistor [J].

Kim, Taehun ;

Lee, Hui Dong ;

Park, Bonghyuk ;

Jang, Seunghyun ;

Kong, Sunwoo ;

Park, Changkun .

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2022, 32 (12) :1443-1446

[30] Design and implementation of a miniaturized high-linearity 3-5 GHz ultrawideband CMOS lownoise amplifier [J].

Lin, Yo-Sheng ;

Yang, Zheng-Hua ;

Chen, Chi- Chen ;

Chao, Tai-Cheng .

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2007, 49 (03) :524-526

← 1 2 3 4 5 →