Investigation of interconnect design on Chip package interaction and mechanical reliability of Cu/low-k multi-layer interconnects in flip chip package

被引：0

作者：

Uchibori, Chihiro J. ^{[1
]}

Zhang, Xuefeng ^{[2
]}

Ho, Paul S. ^{[2
]}

Nakamura, Tomoji ^{[3
]}

机构：

[1] Fujitsu Labs Amer Inc, 1240 E Arques Ave,MS345, Sunnyvale, CA 94085 USA

[2] Univ Texas Austin, Ctr Microelect Res, Austin, TX 78712 USA

[3] Fujitsu Labs LTD, Kanagawa 2430197, Japan

来源：

PROCEEDINGS OF THE IEEE 2008 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Impacts of the interconnect design on the mechanical reliability of Cu/low-k multi-layer interconnects were investigated using Finite Element Analysis. The Chip package interaction (CPI) was analyzed to calculate the energy release rate (ERR). First, impacts of dielectric material properties on CPI were studied using a four metal layer model. Then the study. was extended to seven and nine metal layer models were used to investigate the CPI impacts to crack driving forces. Finally, implications on interconnect design rules and reliabilities will be discussed.

引用

页码：150 / 152

页数：3

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